The ever increasing demands for more efficient power supplies and longer lasting battery-powered electronic devices have made efficiency in power management systems one of the most challenging areas for engineers. Thus, improving the characteristics of discrete power devices, such as power MOSFETs, which are used in power management systems, continue to push manufacturers to produce devices with lower ON-resistance, lower gate charge and higher current capability.
To improve the current carrying capability of a power semiconductor device, such as a trench type power MOSFET, the cell density of the device can be increased. The cell density of the device can be increased by reducing the size of each cell.
Each cell of a power semiconductor device, such as a trench type power MOSFET, includes a trench which receives a gate structure and two source regions each disposed at a respective side of the trench. The width of the trench as well as the lateral expanse of the source regions contribute to the cell pitch. In order to reduce the cell pitch either or both dimensions can be reduced.
A process according to the present invention has the potential for significantly reducing the size of the features in a power device, resulting in increased current carrying capability.
A power MOSFET produced according to an embodiment of the present invention is of a trench variety, in which the active region includes a plurality of trenches each supporting a gate structure and each formed in an epitaxial layer that is grown over a monolithic semiconductor substrate. Formed at the top of each of the trenches are source regions.
According to one aspect of the present invention trenches are formed in a semiconductor body of a first conductivity, a channel region of a second conductivity is then formed in the semiconductor body, gate structures are formed in the trenches, each gate structure including a top oxide layer, dopants of the first conductivity type are implanted into the top oxide layer of each gate structure, a conductive layer of the second conductivity is then formed over the semiconductor body and in contact with the top oxide layer of the gate structures, and, in a thermal step, the dopants of the first conductivity are diffused into the conductive layer of the second conductivity to form conductive regions of the first conductivity, which serve as source regions.
A process according to the present invention is advantageous as it may allow for the formation of source regions having a smaller lateral expanse compared to the prior art. For example, it is believed that 1.0 micron cell pitch can be achieved with 0.5 um photolithography and 0.8 um pitch with 0.35 um lithography. That translates approximately into double the cell density of the conventionally known technology. Higher cell density allows for the possibility of higher current carrying capability and lower RDSON.
That is, a process according to the present invention allows for                Self-aligned source regions;        Improved body contact for better avalanche ruggedness;        Excellent contact of metal to source regions;        Flat silicon surface for better metal coverage;        A four mask process that includes only one critical masking step;        Elimination of the contact mask as a critical masking step (no contacts to the active cells are opened);        Elimination of an insulating layer such as TEOS;        Reduction of the depth of trenches;        Elimination of the need for thick aluminum and TiW barrier layer.        
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.